From 58a89537931cd243c6ddbb9ff435bc5862fc64b0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Jun 2018 22:58:19 +0200 Subject: Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/intel/model_2065x/bootblock.c | 1 - src/cpu/intel/model_206ax/bootblock.c | 1 - 2 files changed, 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index edc2996f05..ed528d1bdd 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -24,7 +24,6 @@ #include #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) -#include #include #include "model_2065x.h" #else diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 90215a496d..670b09750e 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -28,7 +28,6 @@ IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) /* Needed for RCBA access to set Soft Reset Data register */ #include -#include #else #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -- cgit v1.2.3