From 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 Mon Sep 17 00:00:00 2001 From: efdesign98 Date: Thu, 4 Aug 2011 12:09:17 -0600 Subject: Update AMD F14 Agesa to support Rev C0 cpus This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 Reviewed-on: http://review.coreboot.org/131 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/amd/agesa/family14/Makefile.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 3039300976..774d401b63 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -63,9 +63,10 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c @@ -103,6 +104,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c @@ -113,6 +115,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -138,6 +141,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c @@ -213,6 +217,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnCpb.c agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c -- cgit v1.2.3