From a3ce27d3dd65fd937ed9a8c5b9230bcace5b356f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 27 Nov 2019 22:29:44 +0100 Subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SSE2 instructions are supported by family14 and newer. SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/pi/Kconfig | 1 + 2 files changed, 2 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ddfe707d79..9956579c69 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -29,6 +29,7 @@ config CPU_AMD_AGESA select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2 if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index d18f873332..728c7b1ce7 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,6 +28,7 @@ config CPU_AMD_PI select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2 if CPU_AMD_PI -- cgit v1.2.3