From bda870242e16d3406eb1598059b587aee2856dd6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 2 Nov 2019 18:39:44 +0100
Subject: cpu/x86/mtrr/xip_cache.c: Fix inconsistent message

Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/mtrr/xip_cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu')

diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c
index 112c0dfb90..9968eea78e 100644
--- a/src/cpu/x86/mtrr/xip_cache.c
+++ b/src/cpu/x86/mtrr/xip_cache.c
@@ -63,7 +63,7 @@ void platform_prog_run(struct prog *prog)
 	if (cpu_info.x86 == 0xf) {
 		printk(BIOS_NOTICE,
 		       "PROG_RUN: CPU does not support caching ROM\n"
-		       "The next stage will run slowly\n");
+		       "The next stage will run slowly!\n");
 		return;
 	}
 
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