From c82e48d7e4266d2333c78bf7f841e749beec40b8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 17 Apr 2018 11:45:32 -0600 Subject: cpu/x86: add paging_set_default_pat() function Add paging_set_default_pat() which sets up the PAT MSR according to util/x86/x86_page_tables.go. Using page attribute types require a matching of the PAT values with the page table entries. This function is just providing the default PAT MSR value to match against the utility. BUG=b:72728953 Change-Id: I7ed34a3565647ffc359ff102d3f6a59fbc93cc22 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/25715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Justin TerAvest --- src/cpu/x86/pae/pgtbl.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index fe7705f4d0..cd03547ef8 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -144,3 +144,28 @@ void paging_set_pat(uint64_t pat) msr.hi = pat >> 32; wrmsr(MSR_IA32_PAT, msr); } + +/* PAT encoding used in util/x86/x86_page_tables.go. It matches the linux + * kernel settings: + * PTE encoding: + * PAT + * |PCD + * ||PWT PAT + * ||| slot + * 000 0 WB : _PAGE_CACHE_MODE_WB + * 001 1 WC : _PAGE_CACHE_MODE_WC + * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS + * 011 3 UC : _PAGE_CACHE_MODE_UC + * 100 4 WB : Reserved + * 101 5 WP : _PAGE_CACHE_MODE_WP + * 110 6 UC-: Reserved + * 111 7 WT : _PAGE_CACHE_MODE_WT + */ +void paging_set_default_pat(void) +{ + uint64_t pat = PAT_ENCODE(WB, 0) | PAT_ENCODE(WC, 1) | + PAT_ENCODE(UC_MINUS, 2) | PAT_ENCODE(UC, 3) | + PAT_ENCODE(WB, 4) | PAT_ENCODE(WP, 5) | + PAT_ENCODE(UC_MINUS, 6) | PAT_ENCODE(WT, 7); + paging_set_pat(pat); +} -- cgit v1.2.3