From c984f4f30333cde88fbd14a188c5ce599d0fc77c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 29 Jul 2013 10:16:14 +0300 Subject: AMD AGESA: Place CAR_GLOBAL in BSP stack MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use BSP CPU's stack space to store CAR GLOBALS for the duration of romstage before CAR migration. NOTE: Such globals can only be accessed from BSP CPU due the way AMD platform has memory architecture set up. TODO: Add compile-time assertions to verify CAR configuration matches with the programming in vendorcode. Change-Id: Ica4700433268f484ce69a24d934732f9cfd4ba41 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3832 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Bruce Griffith --- src/cpu/amd/agesa/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 142ba8ebdf..9a3f1743a9 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -51,6 +51,18 @@ config UDELAY_LAPIC_FIXED_FSB int default 200 +# TODO: Sync these with definitions in AGESA vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. + +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig -- cgit v1.2.3