From f4c0b596a21918b0d023a39096c99e3d44ef19be Mon Sep 17 00:00:00 2001 From: Indrek Kruusa Date: Wed, 2 Aug 2006 11:30:32 +0000 Subject: Geode LX: this patch adds configuration/status/self-test MSR definitions for L2 cache and fixes wrong P2D defines. This also patch adds L2 cache initialization for Geode LX CPU. Signed-off-by: Indrek Kruusa Signed-off-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_lx/model_lx_init.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c index f7787538a9..ac075eca59 100644 --- a/src/cpu/amd/model_lx/model_lx_init.c +++ b/src/cpu/amd/model_lx/model_lx_init.c @@ -5,7 +5,7 @@ #include #include #include - +#include static void vsm_end_post_smi(void) { @@ -19,9 +19,37 @@ static void vsm_end_post_smi(void) static void model_lx_init(device_t dev) { + + msr_t msr; + printk_debug("model_lx_init\n"); /* Turn on caching if we haven't already */ + + /* Instruction Memory Configuration register + * set EBE bit, required when L2 cache is enabled + */ + msr = rdmsr(CPU_IM_CONFIG); + msr.lo |= 0x400; + wrmsr(CPU_IM_CONFIG, msr); + + /* Data Memory Subsystem Configuration register + * set EVCTONRPL bit, required when L2 cache is enabled in victim mode + */ + msr = rdmsr(CPU_DM_CONFIG0); + msr.lo |= 0x4000; + wrmsr(CPU_DM_CONFIG0, msr); + + /* invalidate L2 cache */ + msr.hi = 0x00; + msr.lo = 0x10; + wrmsr(L2_CONFIG_MSR, msr); + + /* Enable L2 cache */ + msr.hi = 0x00; + msr.lo = 0x0f; + wrmsr(L2_CONFIG_MSR, msr); + x86_enable_cache(); /* Enable the local cpu apics */ -- cgit v1.2.3