From f5cf60f25b8c77e0c90094e3326c5bc0e37cb383 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 18 Mar 2019 15:26:48 +0200 Subject: Move calls to quick_ram_check() before CBMEM init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Werner Zeh --- src/cpu/intel/haswell/romstage.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ee87effc87..0426bb4cea 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -121,9 +120,6 @@ void romstage_common(const struct romstage_params *params) intel_early_me_status(); - quick_ram_check(); - post_code(0x3e); - if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ -- cgit v1.2.3