From bf62b2ddb074c22738b5c9e8dc6c1ecb5d2e5e97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Feb 2015 12:42:51 +0200 Subject: AMD fam10: Drop PCI_BUS_SEGN_BITS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/device/Kconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/device/Kconfig') diff --git a/src/device/Kconfig b/src/device/Kconfig index 42a68d296a..7f43888838 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -259,10 +259,6 @@ config PCIEXP_CLK_PM help Detect and enable Clock Power Management on PCIe. -config PCI_BUS_SEGN_BITS - int - default 0 - config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI -- cgit v1.2.3