From 0cd0d28f0a4a246c0901a5e1f4685205bb683ebd Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Tue, 9 Jun 2015 12:06:20 -0700 Subject: PCIe : Adding some error/not-null condition checking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch checks for following conditions (1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found then don't enable LTR. (2) 2.1) set_L1_ss_latency is member if ops_pci, which could be NULL. so confirm ops_pci is not NULL before calling its member function. 2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency. BUG=none BRANCH=none TEST=build and boot coreboot with L1 substate enabled on sklrvp3. Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315 Signed-off-by: Patrick Georgi Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181 Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447 Original-Signed-off-by: Pratik Prajapati Original-Reviewed-on: https://chromium-review.googlesource.com/276423 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Naveenkrishna Ch Original-Tested-by: Naveenkrishna Ch Reviewed-on: http://review.coreboot.org/10559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/device/pciexp_device.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/device/pciexp_device.c') diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index ee24456747..aa3a457541 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -147,15 +147,20 @@ static void pciexp_config_max_latency(device_t root, device_t dev) { unsigned int cap; cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID); - if (root->ops->ops_pci->set_L1_ss_latency != NULL) - root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4); + if ((cap) && (root->ops->ops_pci != NULL) && + (root->ops->ops_pci->set_L1_ss_latency != NULL)) + root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4); } static void pciexp_enable_ltr(device_t dev) { unsigned int cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - + if(!cap) { + printk(BIOS_INFO, "Failed to enable LTR for dev = %s\n", + dev_path(dev)); + return; + } pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10); } -- cgit v1.2.3