From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/device/pciexp_device.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/device/pciexp_device.c') diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 44b5100742..c20981625e 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -426,19 +426,19 @@ static void pciexp_tune_dev(struct device *dev) return; /* Check for and enable Common Clock */ - if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK)) + if (CONFIG(PCIEXP_COMMON_CLOCK)) pciexp_enable_common_clock(root, root_cap, dev, cap); /* Check if per port CLK req is supported by endpoint*/ - if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM)) + if (CONFIG(PCIEXP_CLK_PM)) pciexp_enable_clock_power_pm(dev, cap); /* Enable L1 Sub-State when both root port and endpoint support */ - if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + if (CONFIG(PCIEXP_L1_SUB_STATE)) pciexp_config_L1_sub_state(root, dev); /* Check for and enable ASPM */ - if (IS_ENABLED(CONFIG_PCIEXP_ASPM)) + if (CONFIG(PCIEXP_ASPM)) pciexp_enable_aspm(root, root_cap, dev, cap); } -- cgit v1.2.3