From 2f48b7b1e9e3d0a631c7d8951c1a5b5dc748df09 Mon Sep 17 00:00:00 2001 From: Youness Alaoui Date: Wed, 24 May 2017 17:47:27 -0400 Subject: pciexp_device: Remove useless write on a read-only register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Role-Based Error Reporting is not a configurable field, it's a read only field in the Device Capability register. This code was old and comes from commit f6eb88ad but evidently is not useful in any way. The PCIe Specification [1] states that it's read-only and must always be set to 1. I have also done tests on purism/librem13 hardware, trying to change that value, without any success. [1]: PCI Express Base Specification Revision 3.0 Page 612 Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399 Signed-off-by: Youness Alaoui Reviewed-on: https://review.coreboot.org/19901 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Martin Roth --- src/device/pciexp_device.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/device') diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index bc8206a6d4..b7ade0ad76 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -361,11 +361,6 @@ static void pciexp_enable_aspm(device_t root, unsigned root_cap, lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); - - /* Enable ASPM role based error reporting. */ - devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); - devcap |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap); } printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); -- cgit v1.2.3