From 909c512c88bd7de4d5c5e7e035f162cd1a039407 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 29 Sep 2015 17:41:30 -0500 Subject: fsp1_1: add verstage support In order to support verstage the cache-as-ram split is taken advantage of such that verstage has the cache-as-ram setup and rosmtage has the cache-as-ram tear down path. The verstage proper just initializes the console and attempts to run romstage which triggers the vboot verification of the firmware. In order to pass the current FSP to use during romstage a global variable in cache-as-ram is populated before returning to the assembly code which tears down cache-as-ram. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados with verstage support as well as VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage. Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11824 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/intel/fsp1_1/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/drivers/intel/fsp1_1/Makefile.inc') diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 78e1006de4..a90e23a0af 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -18,9 +18,14 @@ # Foundation, Inc. # +verstage-y += car.c +verstage-y += fsp_util.c +verstage-y += verstage.c + romstage-y += car.c romstage-y += fsp_util.c romstage-y += hob.c +romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c -- cgit v1.2.3