From 1385b7dd10385e8ae58b4d988701af1eac060fd3 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 5 Apr 2019 13:42:14 +0200 Subject: drivers/intel/fsp1_1: Configure UART after memory init FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/drivers/intel/fsp1_1/include/fsp') diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index e266beec60..d608484999 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -3,6 +3,7 @@ * * Copyright (C) 2014 Google Inc. * Copyright (C) 2015-2016 Intel Corporation + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -91,5 +92,6 @@ void soc_pre_ram_init(struct romstage_params *params); /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, struct mma_config_param *mma_cfg); +void mainboard_after_memory_init(void); #endif /* _COMMON_ROMSTAGE_H_ */ -- cgit v1.2.3