From f4b20af9d716ff57d78d5d576e2990903bd70842 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 20 Feb 2017 13:33:32 -0800 Subject: drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed. BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully. Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/18413 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp1_1/ramstage.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/fsp1_1/ramstage.c') diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index dd1abbeab7..7d9ff8edf0 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -185,11 +185,15 @@ static int fsp_find_and_relocate(struct prog *fsp) return 0; } -void intel_silicon_init(void) +void fsp_load(void) { + static int load_done; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3(); + if (load_done) + return; + if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); @@ -201,7 +205,13 @@ void intel_silicon_init(void) /* FSP_INFO_HEADER is set as the program entry. */ fsp_update_fih(prog_entry(&fsp)); - fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup); + load_done = 1; +} + +void intel_silicon_init(void) +{ + fsp_load(); + fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3()); } /* Initialize the UPD parameters for SiliconInit */ -- cgit v1.2.3