From 3f3025d7f1adc0fa1a405f14a0cbb6e4e319afe0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 18 Aug 2017 15:05:05 +0530 Subject: drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_ENABLE This patch to ensure that coreboot is able to store memory training data into SPI and perform platform lockdown after PCI enumeration is done before handing over control to NotifyPhase() - Post PCI enumeration. Modified coreboot bootstate execution order below: BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration TEST=Please find test case and results for Chrome Devices as Apollolake- Reef, Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS. 1. Without patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Chrome CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. 2. With patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Yocto CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there is no noticeable difference. On a reboot, suspend resume from Chrome console, the mrc cache is found, and utilized. Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/21084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp2_0/notify.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/drivers/intel') diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 63ad37a0dd..34a4262049 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -80,7 +80,7 @@ static void fsp_notify_dummy(void *arg) fsp_notify(END_OF_FIRMWARE); } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, (void *) AFTER_PCI_ENUM); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, (void *) READY_TO_BOOT); -- cgit v1.2.3