From 544878b56349a74e8cb7a0e9af899b5f7fc246fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 9 Aug 2019 11:41:15 +0300 Subject: arch/x86: Add postcar_frame_common_mtrrs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/car.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/drivers/intel') diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index f6e42d7bfa..b206e6d9c3 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -28,13 +28,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ -- cgit v1.2.3