From 2446c1e9e99e6448f5f62c7a4f9c50dceec2b25e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 9 Jul 2020 07:13:37 +0300 Subject: arch/x86: Drop CBMEM_TOP_BACKUP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/drivers') diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416ab7a..29423ef1ba 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -107,3 +107,9 @@ asmlinkage void car_stage_entry(void) { romstage_main(); } + +void *cbmem_top_chipset(void) +{ + /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ + return (void *)restore_top_of_low_cacheable(); +} -- cgit v1.2.3