From 90af720d4e7e6f6d8e3f9fe55e9de0b59abb403d Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Tue, 15 Jan 2019 03:03:16 +0300 Subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b Reviewed-on: https://review.coreboot.org/c/30927 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/spi/sst.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/drivers') diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559969a0ba..63fae95636 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -77,6 +77,11 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { .nr_sectors = 256, .name = "SST25VF080B", .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x80, + .nr_sectors = 256, + .name = "SST25VF080", + .ops = &spi_flash_ops_write_ai, },{ .idcode1 = 0x41, .nr_sectors = 512, @@ -112,6 +117,16 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { .nr_sectors = 128, .name = "SST25WF040", .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x05, + .nr_sectors = 256, + .name = "SST25WF080", + .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x14, + .nr_sectors = 256, + .name = "SST25WF080B", + .ops = &spi_flash_ops_write_ai, }, }; -- cgit v1.2.3