From c57494722319274710533b99692e29510b5cf5ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 16:32:05 +0100 Subject: AGESA,binaryPI: Remove redundant SSE enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/cache_as_ram.S | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e3e5735c3b..e429bba966 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -22,7 +22,6 @@ */ #include "gcccar.inc" -#include #include .code32 @@ -35,15 +34,6 @@ _cache_as_ram_setup: post_code(0xa0) - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa1) - AMD_ENABLE_STACK /* Align the stack. */ -- cgit v1.2.3