From d1371508f525542f3b75de553dc338b9100bde20 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 17 Dec 2019 14:10:16 +0100 Subject: {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which are chipset specific. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook Monolith Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792 Reviewed-by: Frans Hendriks Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 6 +++++- src/drivers/intel/fsp2_0/include/fsp/api.h | 4 +++- src/drivers/intel/fsp2_0/logo.c | 25 ++++++++++++++++--------- src/drivers/intel/fsp2_0/silicon_init.c | 21 +++++++++++---------- 4 files changed, 35 insertions(+), 21 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 824fd0b896..7ce7838642 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -156,10 +156,14 @@ config FSP_PEIM_TO_PEIM_INTERFACE is limited till EFI_PEI_MP_SERVICE_PPI and this option might be useful to add further PPI if required. +config HAVE_FSP_LOGO_SUPPORT + bool + default n + config FSP2_0_DISPLAY_LOGO bool "Enable logo" default n - depends on HAVE_FSP_GOP + depends on HAVE_FSP_LOGO_SUPPORT help Uses the FSP to display the boot logo. This method supports a BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index fb42c7647b..60adb98513 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -70,13 +70,15 @@ uint8_t fsp_memory_mainboard_version(void); uint8_t fsp_memory_soc_version(void); /* Load logo to be displayed by FSP */ -void load_logo(FSPS_UPD *supd); +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ void setup_mma(FSP_M_CONFIG *memory_cfg); +/* Update the SOC specific logo param and load the logo. */ +const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd); /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c index feeec3b995..ba2b5dcbcd 100644 --- a/src/drivers/intel/fsp2_0/logo.c +++ b/src/drivers/intel/fsp2_0/logo.c @@ -11,17 +11,24 @@ * GNU General Public License for more details. */ -#include -#include +#include +#include #include -#include -void load_logo(FSPS_UPD *supd) +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) { - FSP_S_CONFIG *params = &supd->FspsConfig; + const struct cbmem_entry *logo_entry = NULL; + void *logo_buffer; - params->LogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->LogoPtr, - params->LogoSize, CBFS_TYPE_RAW); - if (!params->LogoSize) - params->LogoPtr = 0; + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); + if (logo_entry) { + logo_buffer = cbmem_entry_start(logo_entry); + if (logo_buffer) { + *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, + 1 * MiB, CBFS_TYPE_RAW); + if (logo_size) + *logo_ptr = (UINT32)logo_buffer; + } + } + return (logo_entry); } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ebdbdbf2e6..33d15afad6 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -34,7 +34,7 @@ static void do_silicon_init(struct fsp_header *hdr) fsp_silicon_init_fn silicon_init; uint32_t status; uint8_t postcode; - const struct cbmem_entry *logo_entry; + const struct cbmem_entry *logo_entry = NULL; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); @@ -57,14 +57,9 @@ static void do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); -#if (CONFIG(HAVE_FSP_GOP)) - if (CONFIG(FSP2_0_DISPLAY_LOGO)) { - upd->FspsConfig.LogoSize = 1 * MiB; - logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize); - upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry); - load_logo(upd); - } -#endif + /* Populate logo related entries */ + if (CONFIG(FSP2_0_DISPLAY_LOGO)) + logo_entry = soc_load_logo(upd); /* Call SiliconInit */ silicon_init = (void *) (hdr->image_base + @@ -77,7 +72,7 @@ static void do_silicon_init(struct fsp_header *hdr) timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); - if (CONFIG(FSP2_0_DISPLAY_LOGO)) + if (logo_entry) cbmem_entry_remove(logo_entry); fsp_debug_after_silicon_init(status); @@ -160,3 +155,9 @@ void fsp_silicon_init(bool s3wake) fsps_load(s3wake); do_silicon_init(&fsps_hdr); } + +/* Load bmp and set FSP parameters, fsp_load_logo can be used */ +__weak const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) +{ + return NULL; +} -- cgit v1.2.3