From e993ec7948d874d81c984323b5b00389420a4e65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 20 Mar 2015 08:51:57 +0200 Subject: OxPCIe: Fix UART base addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering Reviewed-by: Patrick Georgi --- src/drivers/uart/oxpcie_early.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index 9daafc5fd9..d560513eb7 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -30,7 +30,6 @@ static unsigned int oxpcie_present CAR_GLOBAL; static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { @@ -79,10 +78,8 @@ static int oxpcie_uart_active(void) uintptr_t uart_platform_base(int idx) { - if (idx == 0 && oxpcie_uart_active()) - return uart0_base; - if (idx == 1 && oxpcie_uart_active()) - return uart1_base; + if ((idx >= 0) && (idx < 8) && oxpcie_uart_active()) + return uart0_base + idx * 0x200; return 0; } @@ -90,7 +87,6 @@ uintptr_t uart_platform_base(int idx) void oxford_remap(u32 new_base) { uart0_base = new_base + 0x1000; - uart1_base = new_base + 0x2000; } void uart_fill_lb(void *data) -- cgit v1.2.3