From e0060a80f0b662f9e4693785baaac16acb96632b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 5 Mar 2020 08:06:27 -0800 Subject: ec/google/chromeec: Fix dev ops for chromeec CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber --- src/ec/google/chromeec/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/ec/google/chromeec/Makefile.inc') diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 2833c87d33..590b131355 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -28,7 +28,7 @@ verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c -- cgit v1.2.3