From bc07f5d93552640793254ce003937ec646120a21 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 26 Mar 2013 13:09:39 -0500 Subject: x86: add rom cache variable MTRR index to tables Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the coreboot tables. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/include/boot/coreboot_tables.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/include/boot') diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index f624ac1e1a..a7e4ab0500 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -250,6 +250,14 @@ struct lb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define LB_TAG_X86_ROM_MTRR 0x0021 +struct lb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. */ + uint32_t index; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ -- cgit v1.2.3