From 33d0fb8d346512e1b6819fa70cb17212ea014336 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 29 Nov 2019 06:38:46 +0200 Subject: AGESA,binaryPI: Add compatibility wrapper for romstage entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This simplifies transition and reviews towards C environment bootblock by allowing single cache_as_ram.S file to be used. Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352 Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/include/cpu/amd/car.h | 9 --------- 1 file changed, 9 deletions(-) delete mode 100644 src/include/cpu/amd/car.h (limited to 'src/include/cpu/amd/car.h') diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h deleted file mode 100644 index f57ea82ad0..0000000000 --- a/src/include/cpu/amd/car.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _CPU_AMD_CAR_H -#define _CPU_AMD_CAR_H - -#include - -asmlinkage void romstage_main(unsigned long bist); -asmlinkage void ap_romstage_main(void); - -#endif -- cgit v1.2.3