From 4e6b7907de07c9c7d4b01a6213a8e13e946398cb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 2 Oct 2018 08:44:47 +0200 Subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/include/cpu/intel/speedstep.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/include/cpu/intel') diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 4b556b758b..5390781304 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -43,7 +43,7 @@ #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_BASE_ADDR 0xe3 #define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee -- cgit v1.2.3