From 5458b9d90a246833de55e0814f0c323a0cf6e471 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 30 Jun 2012 11:41:08 +0300 Subject: Intel cpus: Extend cache to cover complete Flash Device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup would not cover the bottom 4 MB when ramstage is decompressed. Verify CACHE_ROM_SIZE is power of two. One may set CACHE_ROM_SIZE==0 to disable this cache. Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/1146 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle --- src/include/cpu/x86/mtrr.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/include/cpu/x86/mtrr.h') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8b5cc281bc..58bee0412d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,6 +56,12 @@ void x86_setup_fixed_mtrrs(void); # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif + +#define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12) + #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif -- cgit v1.2.3