From 696c642afa8558d7949a13b117066d0a732653fb Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 18 Apr 2018 01:02:47 -0600 Subject: cpu/x86: add limited runtime identity page mapping When employing PAGING_IN_CACHE_AS_RAM more areas need to be mapped in at runtime. Therefore, paging_identity_map_addr() is added to support adding identity mappings. Because there are a fixed amount of pages in cache-as-ram paging only the existing paging structures can be used. As such that's a limitation on what regions and length one can map. Using util/x86/x86_page_tables.go to generate page tables will always populate all the page directory pages. Therefore, 2MiB mappings are easy to map in. BUG=b:72728953 Change-Id: Ibe33aa12972ff678d2e9b80874529380b4ce9fd7 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/25718 Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/include/cpu/x86/pae.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/include/cpu') diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index a8b5e893fc..51e47e1e85 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -32,6 +32,11 @@ void paging_set_default_pat(void); * failure. */ int paging_enable_for_car(const char *pdpt_name, const char *pt_name); +/* Identity map the region indicated by 'base' and 'size'. Both 'base' and + * 'size' need to be 4KiB or 2 MiB aligned. 'pat' should be one of the + * PAT defines above. 0 is returned on success, < 0 on failure. */ +int paging_identity_map_addr(uintptr_t base, size_t size, int pat); + #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); -- cgit v1.2.3