From a75ab2c46d2f7f14511cfa47a716eb394bdb5415 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 28 Dec 2018 17:45:13 +0200 Subject: cpu/intel/car: Drop remains of setup_stack_and_mtrrs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms have moved to POSTCAR_STAGE=y. Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30489 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/include/cpu/intel/romstage.h | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h index 418d029642..726a184eb1 100644 --- a/src/include/cpu/intel/romstage.h +++ b/src/include/cpu/intel/romstage.h @@ -5,23 +5,6 @@ void mainboard_romstage_entry(unsigned long bist); -/* romstage_main is called from the cache-as-ram assembly file. The return - * value is the stack value to be used for romstage once cache-as-ram is - * torn down. The following values are pushed onto the stack to setup the - * MTRRs: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - * ... - */ -void *setup_stack_and_mtrrs(void); - void platform_enter_postcar(void); /* romstage_main is called from the cache-as-ram assembly file to prepare -- cgit v1.2.3