From 7eb0157fca33865783c1cc3c8e5cb2e327e551d7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 21 Sep 2017 08:28:23 +0200 Subject: device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note 4 says bit7 of byte 12 indicates whether the assembly supports self refresh. This patch decodes this and modifies decoding tRR accordingly. Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21620 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki --- src/include/device/dram/ddr2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include/device/dram') diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index ea9b3ba535..288c10298a 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -119,6 +119,8 @@ union dimm_flags_st { unsigned bl4:1; /* DIMM Package is stack */ unsigned stacked:1; + /* the assembly supports self refresh */ + unsigned self_refresh:1; }; unsigned int raw; }; -- cgit v1.2.3