From 492a792d3872ee2683db169fb011daf87b71bff9 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Sat, 6 Mar 2021 10:31:46 -0800 Subject: soc/intel/common/block: Add PCI IDs for EmmitsBurg PCH According to Intel EmmitsBurg EDS, doc# 606161: * Add PCI devid for SPI. * Add PCI devid for ESPI (LPC). EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids Scalable Processor (SPR-SP). Signed-off-by: Reddy Chagam Signed-off-by: Subrata Banik Signed-off-by: Jonathan Zhang Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/include/device/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/include/device') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b54de0bdb2..a3382df4ef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3037,6 +3037,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f +#define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3675,6 +3676,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_SPI1 0x54ab #define PCI_DEVICE_ID_INTEL_ADP_M_SPI2 0x54fb +#define PCI_DEVICE_ID_INTEL_SPR_HWSEQ_SPI 0x1bca + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 -- cgit v1.2.3