From 7f8afe063139f6fc7076a3e4edf6093a953792dc Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 18 Mar 2016 12:21:23 -0500 Subject: arch/x86: introduce postcar stage/phase Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- src/include/rules.h | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'src/include/rules.h') diff --git a/src/include/rules.h b/src/include/rules.h index 6a05ae949c..89fdd21cb2 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -26,6 +26,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "bootblock" #elif defined(__ROMSTAGE__) @@ -35,6 +36,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "romstage" #elif defined(__SMM__) @@ -44,6 +46,7 @@ #define ENV_SMM 1 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "smm" #elif defined(__VERSTAGE__) @@ -53,6 +56,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 1 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "verstage" #elif defined(__RAMSTAGE__) @@ -62,6 +66,7 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "ramstage" #elif defined(__RMODULE__) @@ -71,8 +76,19 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 1 +#define ENV_POSTCAR 0 #define ENV_STRING "rmodule" +#elif defined(__POSTCAR__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 +#define ENV_POSTCAR 1 +#define ENV_STRING "postcar" + #else /* * Default case of nothing set for random blob generation using @@ -86,18 +102,21 @@ #define ENV_SMM 0 #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 +#define ENV_POSTCAR 0 #define ENV_STRING "UNKNOWN" #endif -/* For romstage and ramstage always build with simple device model, ie. - * PCI, PNP and CPU functions operate without use of devicetree. +/* For pre-DRAM stages and post-CAR always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. The reason + * post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's + * no known requirement that devicetree would be needed during that stage. * * For ramstage individual source file may define __SIMPLE_DEVICE__ * before including any header files to force that particular source * be built with simple device model. */ -#if defined(__PRE_RAM__) || defined(__SMM__) +#if defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR #define __SIMPLE_DEVICE__ #endif -- cgit v1.2.3