From 685240610b22f8e5f82204e526c6b8a8d6657173 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 2 Aug 2008 15:15:23 +0000 Subject: Go back to SIPI WAIT state for those CPUS defining the newly introduced CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/x86/lapic.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/include') diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e2c2146942..66b40fc7b6 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -51,6 +51,11 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } + +#if CONFIG_AP_IN_SIPI_WAIT != 1 +/* If we need to go back to sipi wait, we use the long non-inlined version of + * this function in lapic_cpu_init.c + */ static inline __attribute__((always_inline)) void stop_this_cpu(void) { @@ -59,6 +64,7 @@ static inline __attribute__((always_inline)) void stop_this_cpu(void) hlt(); } } +#endif #if ! defined (__ROMCC__) @@ -98,7 +104,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz } -extern inline void lapic_write_atomic(unsigned long reg, unsigned long v) +static inline void lapic_write_atomic(unsigned long reg, unsigned long v) { xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); } -- cgit v1.2.3