From 52919523c14396a8a5dffa34afe40b24b7d68dfc Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 21:44:36 +0200 Subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/51nb/x210/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/51nb') diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index d6ad862c11..b3d9929e2b 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" @@ -144,6 +143,7 @@ chip soc/intel/skylake device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.6 off end # SDXC device pci 1f.0 on chip ec/51nb/npce985la0dx device pnp 0c09.0 on end -- cgit v1.2.3