From 90950925c79b4d0b48c3d9dfc1e3de6a67212a97 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 4 Oct 2009 23:50:06 +0000 Subject: The new CBFS based build system requires the whole ROM to be accessible in very early stages, otherwise the boot may hang like this because the CBFS headers cannot be found/accessed: Uncompressing coreboot to RAM. Jumping to image. Check CBFS header at fffedfe0 magic is ffffffff ERROR: No valid CBFS header found! CBFS: Could not find file fallback/coreboot_ram Jumping to image. This patch enables full ROM access on all 440BX boards right after the serial init (and before CBFS headers are parsed). Build-tested and runtime-tested on ASUS P2B-F. Signed-off-by: Uwe Hermann Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/abit/be6-ii_v2_0/auto.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/abit') diff --git a/src/mainboard/abit/be6-ii_v2_0/auto.c b/src/mainboard/abit/be6-ii_v2_0/auto.c index 70beca92ac..7d323821ff 100644 --- a/src/mainboard/abit/be6-ii_v2_0/auto.c +++ b/src/mainboard/abit/be6-ii_v2_0/auto.c @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ static void main(unsigned long bist) uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); -- cgit v1.2.3