From f333ba09580c00a6f27e3ee0796431f5df936ecf Mon Sep 17 00:00:00 2001 From: Edwin Beasant Date: Thu, 10 Jun 2010 15:24:57 +0000 Subject: This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way. This resolves problems with terminated DRAM modules. Signed-off-by: Edwin Beasant Acked-by: Roland G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/db800/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/amd/db800') diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 893e73dd4a..48b3ede433 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -44,8 +44,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) } #define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 +#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ +#define PLLMSRlo 0x00DE60EE #define DIMM0 0xA0 #define DIMM1 0xA2 @@ -88,7 +88,7 @@ void main(unsigned long bist) pll_reset(ManualConf); - cpuRegInit(); + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); sdram_initialize(1, memctrl); -- cgit v1.2.3