From 3fe3f0409cd340112d62283bf79be9f106a6dff8 Mon Sep 17 00:00:00 2001 From: Justin TerAvest Date: Wed, 14 Feb 2018 19:10:15 -0700 Subject: soc/amd/stoneyridge: Normalize GPIO init This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/amd/gardenia/Makefile.inc | 5 +- src/mainboard/amd/gardenia/bootblock/bootblock.c | 27 +++++++++++ src/mainboard/amd/gardenia/bootblock/gpio.c | 57 ---------------------- src/mainboard/amd/gardenia/gpio.c | 61 ++++++++++++++++++++++++ src/mainboard/amd/gardenia/gpio.h | 22 +++++++++ src/mainboard/amd/gardenia/mainboard.c | 12 ++++- 6 files changed, 124 insertions(+), 60 deletions(-) create mode 100644 src/mainboard/amd/gardenia/bootblock/bootblock.c delete mode 100644 src/mainboard/amd/gardenia/bootblock/gpio.c create mode 100644 src/mainboard/amd/gardenia/gpio.c create mode 100644 src/mainboard/amd/gardenia/gpio.h (limited to 'src/mainboard/amd/gardenia') diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index cceb84c48e..fe3a8c8a46 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -13,13 +13,14 @@ # GNU General Public License for more details. # -bootblock-y += bootblock/gpio.c +bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/OemCustomize.c +bootblock-y += gpio.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c -ramstage-y += bootblock/gpio.c ramstage-y += BiosCallOuts.c +ramstage-y += gpio.c ramstage-y += OemCustomize.c ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c new file mode 100644 index 0000000000..dae59b78d8 --- /dev/null +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "../gpio.h" + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_stoneyridge_gpio *gpios; + gpios = early_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/amd/gardenia/bootblock/gpio.c b/src/mainboard/amd/gardenia/bootblock/gpio.c deleted file mode 100644 index 54d966e251..0000000000 --- a/src/mainboard/amd/gardenia/bootblock/gpio.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* - * As a rule of thumb, GPIO pins used by coreboot should be initialized at - * bootblock while GPIO pins used only by the OS should be initialized at - * ramstage. - */ -const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { - /* NFC PU */ - {GPIO_64, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, - /* PCIe presence detect */ - {GPIO_69, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, - /* MUX for Power Express Eval */ - {GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, - /* SD power */ - {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, -}; - -const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { - /* BT radio disable */ - {GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, - /* NFC wake */ - {GPIO_65, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, - /* Webcam */ - {GPIO_66, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, - /* GPS sleep */ - {GPIO_70, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, -}; - -const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) -{ - if (GPIO_TABLE_BOOTBLOCK) { - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; - } - *size = ARRAY_SIZE(gpio_set_stage_ram); - return gpio_set_stage_ram; -} diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c new file mode 100644 index 0000000000..2d73ee08d2 --- /dev/null +++ b/src/mainboard/amd/gardenia/gpio.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { + /* NFC PU */ + {GPIO_64, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* PCIe presence detect */ + {GPIO_69, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + /* MUX for Power Express Eval */ + {GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, + /* SD power */ + {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, +}; + +const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { + /* BT radio disable */ + {GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* NFC wake */ + {GPIO_65, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* Webcam */ + {GPIO_66, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* GPS sleep */ + {GPIO_70, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, +}; + +const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h new file mode 100644 index 0000000000..f3869448f5 --- /dev/null +++ b/src/mainboard/amd/gardenia/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size); +const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 824fd9d979..71fa257318 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -18,6 +18,9 @@ #include #include #include +#include + +#include "gpio.h" /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -75,7 +78,13 @@ static void pirq_setup(void) picr_data_ptr = mainboard_picr_data; } - +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_stoneyridge_gpio *gpios; + gpios = gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); +} /************************************************* * enable the dedicated function in gardenia board. @@ -90,5 +99,6 @@ static void gardenia_enable(device_t dev) } struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = gardenia_enable, }; -- cgit v1.2.3