From 657d68bddc030e38bc19eb4eef07f59b5e5258e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 12:36:09 +0200 Subject: AGESA,binaryPI: Move PORT80 selection to C bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/amd/lamar/Kconfig | 1 + src/mainboard/amd/lamar/romstage.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/amd/lamar') diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 1d3e0f66a7..d509afcfa9 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON + select DEFAULT_POST_ON_LPC select SUPERIO_FINTEK_F81216H select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 4dde4e2e3f..7f37990efc 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -48,8 +48,6 @@ static void romstage_main_template(void) *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ - hudson_lpc_port80(); - if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); -- cgit v1.2.3