From e6315f74d6f402734e476a57a8faf4ac9cb23d38 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 4 Apr 2020 05:27:05 +0200 Subject: mb/amd/mandolin: Add Picasso CRB Mandolin is the CRB for AMD Picasso and Dali. The mainboard code still needs a little cleanup and verification, but I'll do that in a follow-up to have a non Chromebook board using the Picasso SoC code in tree as soon as possible to be able to detect some possible breakage. BUG=b:130660285 Signed-off-by: Marshall Dawson Signed-off-by: Aaron Durbin Signed-off-by: Zheng Bao Signed-off-by: Felix Held Signed-off-by: Furquan Shaikh Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772 Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/gpio.c | 61 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 src/mainboard/amd/mandolin/gpio.c (limited to 'src/mainboard/amd/mandolin/gpio.c') diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c new file mode 100644 index 0000000000..a60f00e03a --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* SSD DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0, PULL_NONE), + /* Defeature SATA Express DEVSLP, as some boards are reworked + * to tie this to GPIO23 to control power */ + PAD_GPI(GPIO_6, PULL_UP), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* Blink */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* Finger print CS# */ + PAD_GPO(GPIO_31, HIGH), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* Rear camera power enable */ + PAD_GPO(GPIO_89, HIGH), +}; + +/* eMMC controller driving either an SD card or eMMC device. */ +static const struct soc_amd_gpio emmc_gpios[] = { + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_UP), + PAD_NF(GPIO_68, EMMC_CD, PULL_UP), + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP), + PAD_NF(GPIO_105, EMMC_DATA1, PULL_UP), + PAD_NF(GPIO_106, EMMC_DATA2, PULL_UP), + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + PAD_NF(GPIO_74, EMMC_DATA4, PULL_UP), + PAD_NF(GPIO_75, EMMC_DATA6, PULL_UP), + PAD_NF(GPIO_87, EMMC_DATA7, PULL_UP), + PAD_NF(GPIO_88, EMMC_DATA5, PULL_UP), + PAD_NF(GPIO_109, EMMC_DS, PULL_UP), +}; + +void mainboard_program_gpios(void) +{ + program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); + + /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ + if (CONFIG(AMD_LPC_DEBUG_CARD)) + printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); + else + program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios)); +} -- cgit v1.2.3