From a2cfe9e90001fe11f7c7653c9917ea75dd082333 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Thu, 3 Jan 2019 11:38:37 +0200
Subject: amdfam10 boards: Add Makefiles and fix resourcemap.c
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Also remove global ramstage-y += get_bus_conf.c, this is
specific to amdfam10.

Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc  | 4 ++++
 src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c | 6 +++++-
 src/mainboard/amd/serengeti_cheetah_fam10/romstage.c    | 1 -
 3 files changed, 9 insertions(+), 2 deletions(-)

(limited to 'src/mainboard/amd/serengeti_cheetah_fam10')

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
index e826e8153a..c9a38fab7e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
@@ -2,3 +2,7 @@ $(eval $(call asl_template,ssdt2))
 $(eval $(call asl_template,ssdt3))
 $(eval $(call asl_template,ssdt4))
 $(eval $(call asl_template,ssdt5))
+
+romstage-y += resourcemap.c
+
+ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
index 0e47c52784..2a2380a3f9 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
@@ -13,7 +13,11 @@
  * GNU General Public License for more details.
  */
 
-static void setup_mb_resource_map(void)
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
+void setup_mb_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 		/* Careful set limit registers before base registers which contain the enables */
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index fcb10b1daa..03d3484105 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -44,7 +44,6 @@
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
-#include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-- 
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