From b0f1988f893bf5f581917816b11e810309955143 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 9 Jun 2018 11:59:00 +0200 Subject: src: Get rid of unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/amd/tilapia_fam10/devicetree.cb | 4 +-- src/mainboard/amd/tilapia_fam10/dsdt.asl | 38 +++++++++++++-------------- src/mainboard/amd/tilapia_fam10/mainboard.c | 8 +++--- 3 files changed, 25 insertions(+), 25 deletions(-) (limited to 'src/mainboard/amd/tilapia_fam10') diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 77fd875ada..06e33f728d 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 51128bb218..2151222033 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -239,9 +239,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -853,13 +853,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1026,7 +1026,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1049,19 +1049,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1073,7 +1073,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1090,7 +1090,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1121,7 +1121,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1131,7 +1131,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1521,7 +1521,7 @@ DefinitionBlock ( #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1655,7 +1655,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 44c1df69ba..5e112158c2 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -24,8 +24,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ADT7461_ADDRESS 0x4C +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) @@ -150,7 +150,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10); - /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword |= (1 << 26); pci_write_config32(sm_dev, 0xfc, dword); @@ -162,7 +162,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10); - /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); -- cgit v1.2.3