From 036a581b8fa9478d4dba1bf9e576ee9cc0bead24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 20 Nov 2016 07:45:17 +0200 Subject: AGESA f14: Consolidate XIP cache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/amd/union_station/romstage.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/mainboard/amd/union_station') diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index eddcf29fba..cdc564082d 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -39,13 +39,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { -- cgit v1.2.3