From ce6fb1ee2b37193fa828b4c6d475e23c58171346 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 17 Mar 2010 22:44:39 +0000 Subject: Remove failover/fallback/normal handling in mainboards' romstage.c. That's newconfig stuff. 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/mahogany_fam10/romstage.c | 83 +++------------------ src/mainboard/amd/serengeti_cheetah/romstage.c | 82 +++------------------ .../amd/serengeti_cheetah_fam10/romstage.c | 86 +++------------------- 3 files changed, 34 insertions(+), 217 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index eb01aa3375..5846a79301 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -131,80 +131,9 @@ static int spd_read_byte(u32 device, u32 address) #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - int last_boot_normal_flag = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_flag) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sb700_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_flag) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - #if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) - #endif - ; -} -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ - - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if (CONFIG_USE_FAILOVER_IMAGE==0) //#include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" @@ -218,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #define DIMM2 0x52 #define DIMM3 0x53 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -227,6 +156,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sb700_pci_port80(); + } + post_code(0x30); if (bist == 0) { diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 2626f8012a..8c6ea9b72a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -154,82 +154,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node @@ -259,6 +189,16 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct cpuid_result cpuid1; #endif + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 0546a6ddf3..5867fd3506 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -144,88 +144,15 @@ static int spd_read_byte(u32 device, u32 address) #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - int last_boot_normal_flag = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_flag) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_flag) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - #if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) - #endif - ; -} -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ - - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - - #if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -233,6 +160,17 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + post_code(0x30); if (bist == 0) { -- cgit v1.2.3