From ebdc7c7cfebc14d503ab383e1493aa9fd10bd7e8 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Sat, 11 Apr 2009 14:51:49 +0000 Subject: Kill remaining unneeded CAR/ROMCC if-blocks. Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although USE_DCACHE_RAM is always set for them. Such checks are not only pointless, they actively make the files hard to read. A full abuild run confirmed that compilation did not change with this patch applied. The patch does not change whitespace of the remaining code to ease review and svn blame. With this change, it should be possible to have two or three Config.lb variants in total (except the actual hardware config). Right now, some Config.lb have comments, some don't, some have empty lines for better readability, some don't, some have leading whitespace, some don't. This is an utter mess and unifying these files would certainly reduce the headaches I have when looking at them. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/db800/Config.lb | 5 ----- src/mainboard/amd/dbm690t/Config.lb | 16 ---------------- src/mainboard/amd/norwich/Config.lb | 5 ----- src/mainboard/amd/pistachio/Config.lb | 16 ---------------- src/mainboard/amd/serengeti_cheetah/Config.lb | 15 --------------- src/mainboard/amd/serengeti_cheetah_fam10/Config.lb | 14 -------------- 6 files changed, 71 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb index 5b35a06f1a..e4edd27e3e 100644 --- a/src/mainboard/amd/db800/Config.lb +++ b/src/mainboard/amd/db800/Config.lb @@ -50,7 +50,6 @@ if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -58,8 +57,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -108,10 +105,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb index fdff4bd6c9..24316ba6c1 100644 --- a/src/mainboard/amd/dbm690t/Config.lb +++ b/src/mainboard/amd/dbm690t/Config.lb @@ -83,8 +83,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb index b42a98bd6f..3a6fd23edf 100644 --- a/src/mainboard/amd/norwich/Config.lb +++ b/src/mainboard/amd/norwich/Config.lb @@ -52,7 +52,6 @@ end #object reset.o -if USE_DCACHE_RAM #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -60,8 +59,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end -end - ## ## Build our 16 bit and 32 bit coreboot entry code @@ -110,10 +107,8 @@ end ## mainboardinit cpu/x86/fpu/enable_fpu.inc -if USE_DCACHE_RAM mainboardinit cpu/amd/model_lx/cache_as_ram.inc mainboardinit ./cache_as_ram_auto.inc -end ## ## Include the secondary Configuration files diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index 186a60970e..c1f513609e 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -83,8 +83,6 @@ end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o @@ -103,14 +101,12 @@ if USE_DCACHE_RAM end -end ## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -118,7 +114,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -137,12 +132,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -150,12 +143,7 @@ end ### failover to another image. ### if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - else ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc - end end ### @@ -165,16 +153,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb index 039bf4bb05..a0ff3aef73 100644 --- a/src/mainboard/amd/serengeti_cheetah/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -122,8 +122,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -140,7 +138,6 @@ if USE_DCACHE_RAM action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end if USE_FAILOVER_IMAGE else @@ -170,7 +167,6 @@ else end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -178,7 +174,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -207,12 +202,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -221,15 +214,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -240,16 +229,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb index 3689ba2abc..d01785a1cf 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb @@ -129,7 +129,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -149,7 +148,6 @@ if USE_DCACHE_RAM end end -end if USE_FAILOVER_IMAGE else @@ -179,7 +177,6 @@ else end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -187,7 +184,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -217,12 +213,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -231,15 +225,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -250,16 +240,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## -- cgit v1.2.3