From 0ac6b41e70b2df365f8579c6e14214c42ab4c91b Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Tue, 2 Sep 2003 17:16:48 +0000 Subject: - 1.1.4 Major restructuring of hypertransport handling. Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically Updates to hard_reset handling when resetting because of the need to change hypertransport link speeds and widths. (a) No longer assume the boot is good just because we get to a hard reset point. (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the boot counter. Updates to arima/hdama mptable so it tracks the new bus numbers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/arima/hdama/mptable.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'src/mainboard/arima/hdama/mptable.c') diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 856288590d..94ac735744 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -36,40 +36,40 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_processors(mc, processor_map); { - struct pci_dev *dev; - uint32_t base; + device_t dev; + /* 8111 */ - dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } else { - printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n"); + printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 3; bus_isa = 4; } /* 8131-1 */ - dev = dev_find_slot(0, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n"); + printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8131_1 = 1; } /* 8131-2 */ - dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n"); + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); bus_8131_2 = 2; } @@ -85,17 +85,17 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_ioapic(mc, 2, 0x11, 0xfec00000); { - struct pci_dev *dev; + device_t dev; uint32_t base; /* 8131 apic 3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x01,1)); + dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); if (dev) { base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base &= PCI_BASE_ADDRESS_MEM_MASK; smp_write_ioapic(mc, 0x03, 0x11, base); } /* 8131 apic 4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x02,1)); + dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); if (dev) { base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base &= PCI_BASE_ADDRESS_MEM_MASK; -- cgit v1.2.3