From 7dc2864be7fcc342bab0c167997803f5faf147a1 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 13 Jul 2012 19:06:22 +0200 Subject: amd/lx: Move configuration from source to Kconfig LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/artecgroup/dbe61/romstage.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/mainboard/artecgroup/dbe61') diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index f97af920c5..61bd03ee2b 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address) return 0xFF; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -/* CPU and GLIU mult/div 500/266*/ -#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -94,7 +88,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); -- cgit v1.2.3