From 5ff7c13e858a31addf1558731a12cf6c753b576d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 31 Oct 2011 12:56:45 -0700 Subject: remove trailing whitespace Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 50 ++++++------- src/mainboard/asrock/e350m1/BiosCallOuts.h | 4 +- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 18 ++--- .../asrock/e350m1/PlatformGnbPcieComplex.h | 22 +++--- src/mainboard/asrock/e350m1/agesawrapper.c | 84 +++++++++++----------- src/mainboard/asrock/e350m1/agesawrapper.h | 10 +-- src/mainboard/asrock/e350m1/buildOpts.c | 16 ++--- src/mainboard/asrock/e350m1/dimmSpd.c | 16 ++--- src/mainboard/asrock/e350m1/get_bus_conf.c | 18 ++--- src/mainboard/asrock/e350m1/mptable.c | 6 +- 10 files changed, 122 insertions(+), 122 deletions(-) (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index ae67c3fd6e..a0d64a7247 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "agesawrapper.h" #include "amdlib.h" #include "BiosCallOuts.h" @@ -61,7 +61,7 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] = {AGESA_HOOKBEFORE_DQS_TRAINING, BiosHookBeforeDQSTraining }, - + {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, @@ -149,7 +149,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points to the end of the allocated nodes list. */ - + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -199,7 +199,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If BestFitNode is the first buffer in the list, then update StartOfFreedNodes to reflect the new free node - */ + */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { @@ -284,10 +284,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) FreedNodePtr->NextNodeOffset = 0; } else { - /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the size of BIOS_BUFFER_NODE - */ + */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } /* Update StartOfFreedNodes to the new first node */ @@ -295,7 +295,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } else { /* Traverse list of freed nodes to find where the deallocated node should be place - */ + */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { @@ -309,7 +309,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If deallocated node is adjacent to the next node, concatenate both nodes - */ + */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); AllocNodePtr->BufferSize += NextNodePtr->BufferSize; @@ -323,7 +323,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If deallocated node is adjacent to the previous node, concatenate both nodes - */ + */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { @@ -387,10 +387,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT8 Value; UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader; - + ResetType = Data; StdHeader = ConfigPtr; - + // // Perform the RESET based upon the ResetType. In case of // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to @@ -402,17 +402,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) case WARM_RESET_WHENEVER: case COLD_RESET_WHENEVER: break; - + case WARM_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY: Value = 0x06; LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - + default: break; } - + Status = 0; return Status; } @@ -445,10 +445,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT8 Data8; UINT16 Data16; UINT8 TempData8; - + FcnData = Data; MemData = ConfigPtr; - + Status = AGESA_SUCCESS; /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); @@ -459,14 +459,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); TempData8 &= 0x03; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - + Data8 |= BIT2+BIT3; Data8 &= ~BIT4; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -485,7 +485,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) TempData8 &= 0x23; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - + switch(MemData->ParameterListPtr->DDR3Voltage){ case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -527,12 +527,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS Status; UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; - + UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; UINT8 Data8; UINT16 Data16; - + FcnData = Data; ResetInfo = ConfigPtr; // Get SB800 MMIO Base (AcpiMmioAddr) @@ -552,13 +552,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -575,7 +575,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.h b/src/mainboard/asrock/e350m1/BiosCallOuts.h index 2912ec6f51..4efe15fa4d 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.h +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.h @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ @@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* REQUIRED CALLOUTS * AGESA ADVANCED CALLOUTS - CPU - */ + */ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index 0d790773d4..a79dfab62e 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + } }; PCIe_DDI_DESCRIPTOR DdiList [] = { @@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; @@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); + ASSERT(FALSE); return Status; } - + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); @@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - + LibAmdMemFill (BrazosPcieComplexListPtr, 0, sizeof (PCIe_COMPLEX_DESCRIPTOR), @@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { 0, sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - + LibAmdMemFill (BrazosPcieDdiPtr, 0, sizeof (PCIe_DDI_DESCRIPTOR) * 2, @@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index f35d8db723..b51089f7f6 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 802e00e1fe..7fc2fd6da4 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -21,7 +21,7 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - + #include #include #include "agesawrapper.h" @@ -52,8 +52,8 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - +VOID *AcpiAlib = NULL; + /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -64,17 +64,17 @@ VOID *AcpiAlib = NULL; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ -UINT32 +UINT32 agesawrapper_amdinitcpuio ( VOID ) @@ -84,11 +84,11 @@ agesawrapper_amdinitcpuio ( UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - + /* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are @@ -97,21 +97,21 @@ agesawrapper_amdinitcpuio ( PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Map the remaining PCI hole as posted MMIO */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Send all IO (0000-FFFF) to southbridge. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; @@ -122,8 +122,8 @@ agesawrapper_amdinitcpuio ( Status = AGESA_SUCCESS; return (UINT32)Status; } - -UINT32 + +UINT32 agesawrapper_amdinitmmio ( VOID ) @@ -133,7 +133,7 @@ agesawrapper_amdinitmmio ( UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - + /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. @@ -141,27 +141,27 @@ agesawrapper_amdinitmmio ( MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - + /* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. */ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - + /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdinitreset ( VOID ) @@ -169,7 +169,7 @@ agesawrapper_amdinitreset ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -191,14 +191,14 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; - + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); return (UINT32)status; - } - -UINT32 + } + +UINT32 agesawrapper_amdinitearly ( VOID ) @@ -206,7 +206,7 @@ agesawrapper_amdinitearly ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -219,10 +219,10 @@ agesawrapper_amdinitearly ( AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly (AmdEarlyParamsPtr); - + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); @@ -230,7 +230,7 @@ agesawrapper_amdinitearly ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitpost ( VOID ) @@ -272,7 +272,7 @@ agesawrapper_amdinitpost ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitenv ( VOID ) @@ -299,7 +299,7 @@ agesawrapper_amdinitenv ( /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 - */ + */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; PciAddress.Address.Function = 0; @@ -399,17 +399,17 @@ agesawrapper_getlateinitptr ( } } -UINT32 +UINT32 agesawrapper_amdinitmid ( VOID ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - + /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -431,7 +431,7 @@ agesawrapper_amdinitmid ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitlate ( VOID ) @@ -467,10 +467,10 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, + UINT32 Func, + UINT32 Data, VOID *ConfigPtr ) { @@ -499,7 +499,7 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdreadeventlog ( VOID ) diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h index 6d7d9cd196..21e43fe238 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.h +++ b/src/mainboard/asrock/e350m1/agesawrapper.h @@ -21,8 +21,8 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - - + + #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ @@ -66,17 +66,17 @@ typedef struct { * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ - + UINT32 agesawrapper_amdinitreset (void); UINT32 agesawrapper_amdinitearly (void); UINT32 agesawrapper_amdinitenv (void); diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index cde9df7c5f..2707605b9b 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /** * @file * @@ -57,13 +57,13 @@ #define INSTALL_FT1_SOCKET_SUPPORT TRUE #define INSTALL_AM3_SOCKET_SUPPORT FALSE -/* - * Agesa optional capabilities selection. +/* + * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE @@ -104,7 +104,7 @@ #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE @@ -125,10 +125,10 @@ #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -/* - * Agesa configuration values selection. +/* + * Agesa configuration values selection. * Uncomment and specify the value for the configuration options - * needed by the system. + * needed by the system. */ /* The fixed MTRR values to be set after memory initialization. */ diff --git a/src/mainboard/asrock/e350m1/dimmSpd.c b/src/mainboard/asrock/e350m1/dimmSpd.c index 8ef1b4c650..24e2617c0f 100644 --- a/src/mainboard/asrock/e350m1/dimmSpd.c +++ b/src/mainboard/asrock/e350m1/dimmSpd.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "Porting.h" #include "AGESA.h" #include "amdlib.h" @@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) UINT64 limit; address |= 1; // set read bit - + __outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 1, 0x1F); // clear error status __outbyte (iobase + 3, offset); // offset in eeprom @@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer) * * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid + * Optimization relies on autoincrement to avoid * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ @@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); if (error) return error; } - + return 0; } @@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; ioBase = 0xB00; setupFch (ioBase); diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 43867172d5..9746248e87 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -68,22 +68,22 @@ void get_bus_conf(void) * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); + status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } - + sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 397e82995a..960c2c86f1 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -60,11 +60,11 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - + device_t dev; u32 dword; u8 byte; - + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ /* on board NIC & Slot PCIE. */ - + /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); -- cgit v1.2.3