From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/Makefile.inc | 3 ++ src/mainboard/asrock/g41c-gs/early_init.c | 56 +++++++++++++++++++++++++++++++ src/mainboard/asrock/g41c-gs/romstage.c | 55 ------------------------------ 3 files changed, 59 insertions(+), 55 deletions(-) create mode 100644 src/mainboard/asrock/g41c-gs/early_init.c delete mode 100644 src/mainboard/asrock/g41c-gs/romstage.c (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asrock/g41c-gs/Makefile.inc +++ b/src/mainboard/asrock/g41c-gs/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c new file mode 100644 index 0000000000..c7c7b730a6 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) +#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Set GPIOs on superio, enable UART */ + if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { + nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); + pnp_set_logical_device(SERIAL_DEV_R2); + + pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); + pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); + pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); + + nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); + nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); + } else { + winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); + } + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c deleted file mode 100644 index 06e13eb652..0000000000 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) -#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -void mb_lpc_setup(void) -{ - /* Set GPIOs on superio, enable UART */ - if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { - nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); - pnp_set_logical_device(SERIAL_DEV_R2); - - pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); - pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); - pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); - - nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); - nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); - } else { - winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); - } - /* IRQ routing */ - RCBA16(D31IR) = 0x0132; - RCBA16(D29IR) = 0x0237; -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} -- cgit v1.2.3