From edd38465a58d47b737f1e656a8055f64a3b0c421 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 19 Apr 2020 00:55:48 -0400 Subject: mainboard/asus/p3b-f: Reintroduce as variant of p2b Fold this last ASUS 440BX board into the P2B family, while bringing in some changes: - Devicetree becomes overridetree. - Remove non-existent IR device and disable ACPI device on Super I/O to match OEM firmware. - Add SB GPO settings from OEM firmware to devicetree. This disables the SPD enabling magic this board needs. By moving the enabling part to bootblock the hacky enable_spd hook can be eliminated. - Initialize the serial port in bootblock, like the other boards. Boot tested on hardware. Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb (limited to 'src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb') diff --git a/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb b/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb new file mode 100644 index 0000000000..0a608121f6 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb @@ -0,0 +1,12 @@ +chip northbridge/intel/i440bx # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82371eb # Southbridge + register "gpo" = "0x67ffbfff" # GPIO: This value sets GPIOs 27,28 to expose HWM + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.a off end # ACPI + end + end + end + end +end -- cgit v1.2.3