From 1541256f22bbb046a43ccebf73d994d4f4a53374 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 18 Jul 2018 11:48:47 +0200 Subject: mb/asus/p5qc: Add mainboard SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards. Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress) - S3 resume Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR3 fails because the proper clock signal does not get enabled. Even when fixing this it fails later or during memtest, so it should be considered unsupported for now Untested: - PCIe x1 ports (expected to work) - sound (expected to work) TODO: add documentation Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/28264 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asus/p5qc/acpi/platform.asl | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 src/mainboard/asus/p5qc/acpi/platform.asl (limited to 'src/mainboard/asus/p5qc/acpi/platform.asl') diff --git a/src/mainboard/asus/p5qc/acpi/platform.asl b/src/mainboard/asus/p5qc/acpi/platform.asl new file mode 100644 index 0000000000..6c92a4ed47 --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} -- cgit v1.2.3